In recent years, along with the popularization of portable devices such as mobile telephones, a need has arisen to operate a microprocessor at low power consumption for a long time, and attention has been drawn to a technology for prolonging battery life, and dynamically changing an operation clock of the microprocessor in accordance with its operation mode to achieve low power consumption. However, promotion of a low speed of a clock frequency has increased effects on the portable devices. For example, a DRAM which is a mainstream memory at present must be refreshed by a fixed frequency or higher, and thus it cannot be operated by an extremely low speed clock of this frequency or lower.
FIG. 1 shows an example of a conventional microprocessor having an extremely low speed mode. A central processing unit (CPU) 415, a dynamic random access memory (DRAM) 402, static random access memory (SRAM) 403, an interrupt control circuit 416, and a clock control circuit incorporating a clock mode designation register 405 are connected to a data bus 401. A not-shown read-only memory (ROM) is also connected.
As the DRAM 402 holds data by using a very small capacitor, the data is lost unless a refresh operation is periodically executed to save the data. If there is a lowest clock frequency for this refreshing, and a supplied clock frequency is lower than the clock lowest frequency, the DRAM 402 must be operated in a self-refresh mode to hold the data.
The SRAM 403 is operated at a low speed by low voltage. However, the price of using such SRAM is high because of a large pattern area per bit, and there is a limit, i.e., only a small-capacity SRAM can be loaded on a chip such as a microprocessor.
A command queue 404 is normally first in, first out (FIFO), stores commands to be executed in order, and sends a command to be executed next to a command register IR 406. A program counter 409 is a register for designating an address of the command to be executed next, and counts in accordance with the number of bytes of the command. The address is outputted to an address bus 410, and an address DramAdr of the DRAM 402 and an address SramAdr of the SRAM 403 are supplied. An address RomAdr of the ROM is also supplied.
Normally, as a method for switching the DRAM 402 to an extremely low speed mode, there is a method for setting a value corresponding to an operation mode in the clock mode designation register 405 to change the mode of the CPU to the extremely low speed mode using the clock control circuit 407. Upon reception of the designation, the clock control circuit 407 supplies a clock of a frequency corresponding to the designation to each part of the microcontroller. After the clock control circuit 407 enters an extremely low speed clock mode designation signal ModeReq to a DRAM control circuit 408, the DRAM control circuit 408 switches the DRAM to a self-refresh mode.
The interrupt control circuit 416 receives an internally or externally generated interrupt request signal IntReq, and then outputs an interrupt signal Int to the CPU 415. Upon receipt of the request, the CPU 415 jumps to an interrupt processing routine to execute processing in accordance with an interrupt factor thereof. Regarding interrupt factors, interruption by an internal factor, for example interruption when a command inexcutable because of a memory abnormality is executed, or interruption by an external factor, for example timer interruption, interruption from a keyboard or the like, is conceivable. Here, the interruption is used to return the CPU 415 from an extremely low speed operation mode to a normal operation mode.
Now, description is made of a process until the conventional microcontroller shown in FIG. 1 is operated by an extremely low speed clock. FIG. 2 is a conceptual diagram showing an address space where the conventional microcontroller of FIG. 1 is operated. In FIG. 2, in the address space, addresses start from a lowest address of 0x000, and a highest address is 0xffff. A program originally placed on the ROM is copied in the DRAM by a loader, and executed at a high speed. However, as the DRAM is switched to a self-refresh mode by an extremely low speed clock, execution of the program becomes impossible. Thus, to switch to an extremely low speed mode, the operation is jumped to an extremely low speed mode switching routine in the SRAM 403. That is, the operation is jumped from an address DramAdr of a jump command in the DRAM to a head address SramAdr of the extremely low speed mode switching routine in the SRAM. In the extremely low speed mode switching routine, processing necessary for the switch is executed, and the program is executed in the SRAM until the mode is released. Thus, the program in the SRAM can be set to be identical to the program in the DRAM. The extremely low speed mode can be released by a command in the SRAM, or an interrupt routine for the CPU 415. However, this interrupt routine must be loaded on the SRAM. Another method for switching to an extremely low speed mode is to jump an operation to a ROM operated even by an extremely low speed clock. In this case, the operation is jumped to a head address RomAdr of a corresponding processing routine in the ROM.
For the conventional extremely low speed mode, the SRAM 403 that often has been used has been high in price, low in capacity, and unloadable on the chip. Even if copies of almost all the programs in the DRAM can be loaded on the SRAM 403, the capacity of the SRAM consumed becomes impractically high. In addition, a method of installing the SRAM outside the microcontroller is expensive to execute, and a system for carrying it out becomes complex. Use of a ROM in this respect is inexpensive, and a high capacity is easily achieved.
However, in all of the above-described methods, a considerable number of processing steps must be executed to switch between the extremely low speed mode and the normal mode and, therefore, immediacy is lost. This is described more in detail by way of a specific example. According to this example, if there is a need to take out data because of an external factor (high speed data reception) during operation in an extremely low speed mode, interrupt processing is executed to return to a normal operation mode, and then data is received by an operation in the normal mode. In this case, until the return to the normal mode (e.g., operation mode by a clock of 20 MHz), a program is executed in an extremely low speed mode (e.g., operation mode by a clock of 2 MHz). Thus, assuming that an interrupt processing routine is constituted of thirty steps, and processing to return to the normal mode is constituted of twenty steps, 25 μs are expended in the extremely low speed mode. If there are serial communications executed at 500 Kbps (data cycle 20 μs when a data length is 8 bits, and each of start and stop bits is 1), communication errors occur on the extremely low speed mode.
Thus, if the conventional processing for operation mode switching between the extremely low speed mode and the normal operation mode is executed by software interrupt processing, immediacy is lost to complete processing in time, creating a problem of erroneous operations.